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19-0869; Rev 0; 8/07
Complete, Direct-Conversion Tuner for DVB-S2 Applications
General Description
The MAX2112 low-cost, direct-conversion tuner IC is designed for satellite set-top and VSAT applications. The IC is intended for 8PSK and Digital Video Broadcast (DVB-S2) applications. The MAX2112 directly converts the satellite signals from the LNB to baseband using a broadband I/Q downconverter. The operating frequency range extends from 925MHz to 2175MHz. The device includes an LNA and an RF variable-gain amplifier, I and Q downconverting mixers, and baseband lowpass filters with programmable cutoff frequency control and digitally controlled baseband variable-gain amplifiers. Together, the RF and baseband variable-gain amplifiers provide more than 80dB of gain control range. The IC is compatible with virtually all DVB-S2 demodulators. The MAX2112 includes fully monolithic VCOs, as well as a complete fractional-N frequency synthesizer. Additionally, an on-chip crystal oscillator is provided along with a buffered output for driving additional tuners and demodulators. Synthesizer programming and device configuration are accomplished with a 2-wire serial interface. The IC features a VCO autoselect (VAS) function that automatically selects the proper VCO. For multituner applications, the device can be configured to have one of two 2-wire interface addresses. A low-power standby mode is available whereupon the signal path is shut down while leaving the reference oscillator, digital interface, and buffer circuits active, providing a method to reduce power in single and multituner applications. The MAX2112 is the most advanced DBS tuner available today. The low noise figure eliminates the need for an external LNA. A small number of passive components are needed to form a complete DVB-S2 RF frontend solution. The tuner is available in a very small 28-pin thin QFN package.
Features
925MHz to 2175MHz Frequency Range Monolithic VCO Low Phase Noise: -97dBc/Hz at 10kHz No Calibration Required High Dynamic Range: -75dBm to 0dBm Integrated Variable BW LP Filters: 4MHz to 40MHz Single +3.3V 5% Supply Low-Power Standby Mode Multiple 2-Wire Addresses for Multituner Applications Differential I/Q Interface I2C 2-Wire Serial Interface Very Small 28-Pin TQFN Package
MAX2112
Ordering Information
PART MAX2112CTI+ MAX2112ETI+ TEMP RANGE PIN-PACKAGE 0C to +70C PKG CODE
28 Thin QFN-EP* T2855+3
-40C to +85C 28 Thin QFN-EP* T2855+3
*EP = Exposed paddle. +Denotes a lead-free package.
Pin Configuration/ Functional Diagram
VCC_BB ADDR QDC+ QDCSDA IDC22 21 IDC+ SCL 27
+
VCC_RF2 1
28
26
25
24
23
INTERFACE LOGIC AND CONTROL VCC_RF1 2
MAX2112
LPF BW CONTROL
DC OFFSET CORRECTION
Applications
DirecTV and Dish Network DBS DVB-S2 VSATs
20
IOUT-
GND
3
19
IOUT+
RFIN
4 5 DIV2/DIV4 FREQUENCY SYNTHESIZER
18
QOUT-
GC1
17
QOUT+
VCC_LO
6
EP
16
VCC_DIG
VCC_VCO
7 8 VCOBYP 9 VTUNE 10 GNDTUNE 11 GNDSYN 12 CPOUT 13 VCC_SYN 14 XTAL
15
REFOUT
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Complete, Direct-Conversion Tuner for DVB-S2 Applications MAX2112
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +3.9V All Other Pins to GND.................................-0.3V to (VCC + 0.3V) RF Input Power: RFIN .....................................................+10dBm VCOBYP, CPOUT, XTAL, REFOUT, IOUT_, QOUT_ , IDC_, QDC_ to GND Short-Circuit Protection...............................10s Continuous Power Dissipation (TA = +70C) 28-Pin Thin QFN (derated 34.5mW/C above +70C) ...2.75W Operating Temperature Range (MAX2112CTI+) ......0C to +70C Operating Temperature Range (MAX2112ETI+) ...-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +160C Soldering Temperature (10s) ...........................................+260C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION! ESD SENSITIVE DEVICE
DC ELECTRICAL CHARACTERISTICS
(MAX2112 Evaluation Kit: VCC = +3.13V to +3.47V, TA = 0C to +70C (MAX2112CTI+), TA = -40C to +85C (MAX2112ETI+), VGC1 = +0.5V (max gain), default register settings except ICP = 1 and BBG[3:0] = 1011. No input signals at RF, baseband I/Os are open circuited. Typical values measured at VCC = +3.3V, TA = +25C.) (Note 1)
PARAMETER SUPPLY Supply Voltage Supply Current Receive mode, bit STBY = 0 Standby mode, bit STBY = 1 2.4 0.5 50 -50 Maximum gain = 0.5V 0.5 -50 0.4 2.7 +50 2.3 400 0.7 x VCC 0.3 x VCC Digital inputs = GND or VCC ISINK = 1mA 0.1 1 0.4 3.13 3.3 100 3 3.47 160 V mA CONDITIONS MIN TYP MAX UNITS
ADDRESS SELECT INPUT (ADDR) Digital Input Voltage High, VIH Digital Input Voltage Low, VIL Digital Input Current High, IIH Digital Input Current Low, IIL ANALOG GAIN-CONTROL INPUTS (GC) Input Voltage Range Input Bias Current VCO TUNING VOLTAGE INPUT (VTUNE) Input Voltage Range 2-WIRE SERIAL INPUTS (SCL, SDA) Clock Frequency Input Logic-Level High Input Logic-Level Low Input Leakage Current 2-WIRE SERIAL OUTPUT (SDA) Output Logic-Level Low V kHz V V A V V A V V A A
2
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Complete, Direct-Conversion Tuner for DVB-S2 Applications
AC ELECTRICAL CHARACTERISTICS
(MAX2112 Evaluation Kit: VCC = +3.13V to +3.47V, TA = 0C to +70C (MAX2112CTI+), TA = -40C to +85C (MAX2112ETI+), default register settings except ICP = 1 and BBG[3:0]=1011. Typical values measured at VCC = +3.3V, TA = +25C.) (Note 1)
PARAMETER MAIN SIGNAL PATH PERFORMANCE Input Frequency Range RF Gain-Control Range (GC1) Baseband Gain-Control Range In-Band Input IP3 Out-of-Band Input IP3 Input IP2 Adjacent Channel Protection (Note 2) 0.5V < VGC1 < 2.7V Bits GC2 = 1111 to 0000 (Note 3) (Note 4) (Note 5) (Note 6) VGC1 is set to 0.5V (maximum RF gain) and BBG[3:0] is adjusted to give a 1VP-P baseband output level for a -75dBm CW input tone at 1500MHz Starting with the same BBG[3:0] setting as above, VGC1 is adjusted to back off RF gain by 10dB (Note 7) Minimum RF Input Return Loss Nominal Output Voltage Swing I/Q Amplitude Imbalance I/Q Quadrature Phase Imbalance Output 1dB Compression Voltage Baseband Highpass -3dB Frequency Corner BASEBAND LOWPASS FILTERS Filter Bandwidth Range Rejection Ratio Group Delay Ratio of In-Filter-Band to Out-ofFilter-Band Noise FREQUENCY SYNTHESIZER RF-Divider Frequency Range RF-Divider Range (N) Reference-Divider Frequency Range Reference-Divider Range (R) Phase-Detector Comparison Frequency VOLTAGE-CONTROLLED OSCILLATOR AND LO GENERATION Guaranteed LO Frequency Range fOFFSET = 10kHz LO Phase Noise fOFFSET = 100kHz fOFFSET = 1MHz 925 -97 -100 -122 dBc/Hz 2175 MHz 925 19 12 1 12 2175 251 30 1 30 MHz MHz MHz At 2 x f-3dB Up to 1dB bandwidth fINBAND = 100Hz to 22.5MHz, fOUTBAND = 87.5MHz to 112.5MHz 4 39 37 25 40 MHz dB ns dB 925MHz < fRF < 2175MHz, in 75 system RLOAD = 2k//10pF Measured at 500kHz; filter set to 22.27MHz Measured at 500kHz; filter set to 22.27MHz 30 3.3 400 Differential 47nF capacitors at IDC_, QDC_ 0.5 BASEBAND OUTPUT CHARACTERISTICS 1 1 3.5 VP-P dB Degrees VP-P Hz 925 65 13 73 15 +2 +15 +40 25 8 dB 9 12 12 dB 2175 MHz dB dB dBm dBm dBm dB CONDITIONS MIN TYP MAX UNITS
MAX2112
Noise Figure
Single-Ended I/Q Output Impedance Real ZO, from 1MHz to 40MHz
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Complete, Direct-Conversion Tuner for DVB-S2 Applications MAX2112
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2112 Evaluation Kit: VCC = +3.13V to +3.47V, TA = 0C to +70C (MAX2112CTI+), TA = -40C to +85C (MAX2112ETI+), default register settings except ICP = 1 and BBG[3:0]=1011. Typical values measured at VCC = +3.3V, TA = +25C.) (Note 1)
PARAMETER XTAL Oscillator Frequency Range Input Overdrive level XTAL Output-Buffer Divider Range XTAL Output Voltage Swing XTAL Output Duty Cycle 4MHz to 30MHz, CLOAD = 10pF CONDITIONS Parallel-resonance-mode crystal AC-coupled sine-wave input MIN 12 0.5 1 1 1.5 50 1 TYP MAX 30 2.0 8 2 VP-P % UNITS MHz VP-P
XTAL/REFERENCE OSCILLATOR INPUT AND OUTPUT BUFFER
Note 1: MAX2112CTI+: Min/max values are production tested at TA = +70C. Min/max limits at TA = 0C and TA = +25C are guaranteed by design and characterization. MAX2112ETI+: Min/max values are production tested at TA = +85C. Min/max limits at TA = -40C and TA = +25C are guaranteed by design and characterization. Note 2: Input gain range specifications met over this band. Note 3: In-band IIP3 test conditions: GC1 set to provide the nominal baseband output drive when mixing down a -23dBm tone at 2175MHz to 5MHz baseband (fLO = 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at -26dBm each are applied at 2174MHz and 2175MHz. The IM3 tone at 3MHz is measured at baseband, but is referred to the RF input. Note 4: Out-of-band IIP3 test conditions: GC1 set to provide nominal baseband output drive when mixing down a -23dBm tone at 2175MHz to 5MHz baseband (fLO = 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at -20dBm each are applied at 2070MHz and 1975MHz. The IM3 tone at 5MHz is measured at baseband, but is referred to the RF input. Note 5: Input IP2 test conditions: GC1 set to provide nominal baseband output drive when mixing down a -23dBm tone at 2175MHz to 5MHz baseband (fLO = 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at -20dBm each are applied at 925MHz and 1250MHz. The IM2 tone at 5MHz is measured at baseband, but is referred to the RF input. Note 6: Adjacent channel protection test conditions: GC1 is set to provide the nominal baseband output drive with a 2110MHz 27.5Mbaud signal at -55dBm. GC2 set for mid-scale. The test signal shall be set for PR = 7/8 and SNR of -8.5dB. An adjacent channel at 40MHz is added at -25dBm. DVB-S BER performance of 2E-4 shall be maintained for the desired signal. GC2 may be adjusted for best performance. Note 7: Guaranteed by design and characterization at TA = +25C.
4
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Complete, Direct-Conversion Tuner for DVB-S2 Applications
Typical Operating Characteristics
(MAX2112 Evaluation Kit: VCC = +3.3V, TA = +25C, baseband output frequency = 5MHz; VGC1 = +1.2V, default register settings except ICP = 1 and BBG[3:0] = 1011.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX2112 toc01
MAX2112
STANDBY MODE SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX2112 toc02
SUPPLY CURRENT vs. BASEBAND FILTER CUTOFF FREQUENCY
102 100 SUPPLY CURRENT (mA) 98 96 94 92 90 88 86 84
MAX2112 toc03
98 97 96 SUPPLY CURRENT (mA) 95 94 93 92 91 90 89 88 3.0 3.1 3.2 3.3 3.4 3.5 TA = -40C TA = +25C TA = +85C
3.0 2.9 TA = +85C SUPPLY CURRENT (mA) 2.8 2.7 2.6 2.5 2.4 2.3 TA = -40C TA = +25C
104
3.6
3.0
3.1
SUPPLY VOLTAGE (V)
3.2 3.3 3.4 SUPPLY VOLTAGE (V)
3.5
3.6
4
8
12
16
20
24
28
32
36
40
BASEBAND FILTER CUTOFF FREQUENCY (MHz)
HD3 vs. VOUT
MAX2112 toc04
QUADRATURE PHASE vs. LO FREQUENCY
MAX2112 toc05a
QUADRATURE MAGNITUDE MATCHING vs. LO FREQUENCY
QUADRATURE MAGNITUDE MATCHING (%) 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 900 1200 1500 1800 2100 2400 TA = -40C TA = +85C fBASEBAND = 10MHz TA = +25C
MAX2112 toc05b
-10 BASEBAND 3RD-ORDER HARMONIC (dBc) -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 1.0 1.5 2.0 2.5 3.0
93.5 fBASEBAND = 10MHz 92.5 QUADRATURE PHASE () TA = +25C 91.5 90.5 89.5 88.5 87.5 86.5 TA = -40C TA = +85C
1.0
3.5
900
1200
VOUT (VP-P)
1500 1800 2100 LO FREQUENCY (MHz)
2400
LO FREQUENCY (MHz)
QUADRATURE PHASE vs. BASEBAND FREQUENCY
MAX2112 toc06a
QUADRATURE MAGNITUDE MATCHING vs. BASEBAND FREQUENCY
QUADRATURE MAGNITUDE MATCHING (dB) 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 4 8 12 16 20 TA = +25C TA = -40C TA = +85C fLO = 925MHz
MAX2112 toc06b
BASEBAND FILTER FREQUENCY RESPONSE
-10 BASEBAND OUTPUT LEVEL (dB) -20 -30 -40 -50 -60 -70 -80 0 20 40 60 80
MAX2112 toc07
93.5 fLO = 925MHz 92.5 QUADRATURE PHASE () TA = +85C 91.5 90.5 89.5 88.5 87.5 86.5 0 4 8 12 16 TA = +25C TA = -40C
1.0
0
20
BASEBAND FREQUENCY (MHz)
BASEBAND FREQUENCY (MHz)
BASEBAND FREQUENCY (MHz)
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Complete, Direct-Conversion Tuner for DVB-S2 Applications MAX2112
Typical Operating Characteristics (continued)
(MAX2112 Evaluation Kit: VCC = +3.3V, TA = +25C, baseband output frequency = 5MHz; VGC1 = +1.2V, default register settings except ICP = 1 and BBG[3:0] = 1011.)
BASEBAND FILTER HIGHPASS FREQUENCY RESPONSE
MAX2112 toc08
PROGRAMMED f-3dB FREQUENCY vs. MEASURED f-3dB FREQUENCY
MAX2112 toc09
BASEBAND FILTER 3dB FREQUENCY vs. TEMPERATURE
0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 NORMALIZED TO TA = +25C
MAX2112 toc10
2 0 BASEBAND OUTPUT LEVEL (dB) -2 -4 -6 -8 -10 -12 -14 100 1000 BASEBAND FREQUENCY (MHz)
45 LPF[7:0] = 12 + (f-3dB - 4MHz) / 290kHz MEASURED f-3dB FREQUENCY (MHz) 40 35 30 25 20 15 10 5 0
1.0 BASEBAND GAIN ERROR AT f-3dB (dB)
10,000
0
5
10
15
20
25
30
35
40
45
-40
-20
PROGRAMMED f-3dB FREQUENCY (MHz)
0 20 40 TEMPERATURE (C)
60
80
INPUT POWER vs. VGC1
MAX2112 toc11
NOISE FIGURE vs. FREQUENCY
MAX2112 toc12
NOISE FIGURE vs. INPUT POWER
ADJUST BBG[3:0] FOR 1VP-P BASEBAND OUTPUT WITH PIN = -75dBm AND VGC1 = 0.5V. fLO = 1500MHz
MAX2112 toc13
10 0 -10 INPUT POWER (dBm) -20 -30 -40 -50 -60 TA = -40C TA = +85C ADJUST BBG[3:0] FOR 1VPP BASEBAND OUTPUT WITH PIN = -75dBm AND VGC1 = 0.5V TA = +25C
10.5 10.0 NOISE FIGURE (dB) 9.5 9.0 8.5 8.0 TA = +25C ADJUST BBG[3:0] FOR 1VPP BASEBAND OUTPUT WITH PIN = -75dBm AND VGC1 = 0.5V TA = +85C TA = +70C
70 60 NOISE FIGURE (dB) 50 40 30 20 10 0
-70 -80 0.5 1.0 1.5 2.0 VGC1 (V) 2.5 3.0 7.5 900 1100 1300 1500 1700 1900 2100 2300 FREQUENCY (MHz)
-80
-70
-60
-50
-40 -30
-20 -10
0
INPUT POWER (dBm)
OUT-OF-BAND IIP3 vs. INPUT POWER
MAX2112 toc14
IN-BAND IIP3 vs. INPUT POWER
MAX2112 toc15
IIP2 vs. INPUT POWER
SEE NOTE 5 ON PAGE 4 FOR CONDITIONS 50 40
MAX2112 toc16
30 SEE NOTE 4 ON PAGE 4 FOR CONDITIONS 20 OUT-OF-BAND IIP3 (dBm) 10 0 -10 -20
30 SEE NOTE 3 ON PAGE 4 FOR CONDITIONS 20 10 IN-BAND IIP3 (dBm) 0
60
IIP2 (dBm)
-10 -20 -30 -40 -50
30 20 10 0 -10
-30 -80 -70 -60 -50 -40 -30 -20 -10 0 INPUT POWER (dBm)
-60 -80 -70 -60 -50 -40 -30 -20 -10 0 INPUT POWER (dBm)
-80
-70
-60
-50
-40 -30
-20 -10
0
INPUT POWER (dBm)
6
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Complete, Direct-Conversion Tuner for DVB-S2 Applications
Typical Operating Characteristics (continued)
(MAX2112 Evaluation Kit: VCC = +3.3V, TA = +25C, baseband output frequency = 5MHz; VGC1 = +1.2V, default register settings except ICP = 1 and BBG[3:0] = 1011.)
INPUT RETURN LOSS vs. FREQUENCY
MAX2112 toc17
MAX2112
0
PHASE NOISE AT 10kHz OFFSET vs. CHANNEL FREQUENCY
PHASE NOISE AT 10kHz OFFSET (dBc/Hz)
MAX2112 toc18
-90
INPUT RETURN LOSS (dB)
-5 VGC1 = 0.5V
-10
-95
-15
-100
-20 VGC1 = 2.7V 900 1125 1350 1575 1800 2025 2250 FREQUENCY (MHz)
-25
-105 925 1115 1305 1495 1685 1875 2065 2255 CHANNEL FREQUENCY (MHz)
PHASE NOISE vs. OFFSET FREQUENCY
MAX2112 toc19
LO LEAKAGE vs. LO FREQUENCY
MEASURED AT RF INPUT -75
MAX2112 toc20
-70 fLO = 1800MHz -80 PHASE NOISE (dBc/Hz) -90 -100 -110 -120 -130 1.0E+02
-70
LO LEAKAGE (dBm) 1.0E+03 1.0E+04 1.0E+05 OFFSET FREQUENCY (Hz) 1.0E+06
-80
-85
-90 925 1175 1425 1675 1925 LO FREQUENCY (MHz) 2175
VCO: KV vs. VTUNE
400 350 300 KV (MHz/V) 250 200 150 100 50 0 0 0.5 1.0 1.5 2.0 VTUNE (V) 2.5 3.0 SUB-BAND 0 SUB-BAND 12 SUB-BAND 23
MAX2112 toc21
450
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Complete, Direct-Conversion Tuner for DVB-S2 Applications MAX2112
Pin Description
PIN 1 2 3 4 5 NAME VCC_RF2 VCC_RF1 GND RFIN GC1 DESCRIPTION DC Power Supply for LNA. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections. DC Power Supply for LNA. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections. Ground. Connect to board's ground plane for proper operation. Wideband 75 RF Input. Connect to an RF source through a DC-blocking capacitor. RF Gain-Control Input. High-impedance analog input with a 0.5V to 2.7V operating range. VGC1 = 0.5V corresponds to the maximum gain setting. DC Power Supply for LO Generation Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections. DC Power Supply for VCO Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections. Internal VCO Bias Bypass. Bypass to GND with a 100nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections. High-Impedance VCO Tune Input. Connect the PLL loop filter output directly to this pin with as short of a connection as possible. Ground for VTUNE. Connect to the PCB ground plane. Ground for Synthesizer. Connect to the PCB ground plane. C h ar g e - P ump O u tp u t . Co n n e c t t h is o u t p u t t o t he P L L lo o p filt e r in p u t w it h th e sh or t e st c o n n e ct io n p o ssib le . DC Power Supply for Synthesizer Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections. Crystal-Oscillator Interface. Use with an external parallel-resonance-mode crystal through a series 1nF capacitor. See the Typical Application Circuit. Crystal-Oscillator Buffer Output. A DC-blocking capacitor must be used when driving external circuitry. DC Power Supply for Digital Logic Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections. Quadrature Baseband Differential Output. AC-couple with 47nF capacitors to the demodulator input. In-Phase Baseband Differential Output. AC-couple with 47nF capacitors to the demodulator input. I-Channel Baseband DC Offset Correction. Connect a 47nF ceramic chip capacitor from IDC- to IDC+. Q-Channel Baseband DC Offset Correction. Connect a 47nF ceramic chip capacitor from QDC- to QDC+. DC Power Supply for Baseband Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections.
6
VCC_LO
7
VCC_VCO
8 9 10 11 12
VCOBYP VTUNE GNDTUNE GNDSYN CPOUT
13
VCC_SYN
14 15
XTAL REFOUT
16 17 18 19 20 21 22 23 24 25
VCC_DIG QOUT+ QOUTIOUT+ IOUTIDC+ IDCQDC+ QDCVCC_BB
8
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Complete, Direct-Conversion Tuner for DVB-S2 Applications
Pin Description (continued)
PIN 26 27 28 -- NAME SDA SCL ADDR EP DESCRIPTION 2-Wire Serial-Data Interface. Requires a 2.7k pullup resistor to VCC. 2-Wire Serial-Clock Interface. Requires a 2.7k pullup resistor to VCC. Address. Must be connected to either ground (logic 0) or supply (logic 1). Exposed Paddle. Solder evenly to the board's ground plane for proper operation.
MAX2112
Detailed Description
Register Description
The MAX2112 includes 12 user-programmable registers and 2 read-only registers. See Table 1 for register
configurations. The register configuration of Table 1 shows each bit name and the bit usage information for all registers. Note that all registers must be written after and no earlier than 100s after the device is powered up.
Table 1. Register Configuration
MSB REG REGISTER READ/ REG NUMBER NAME WRITE ADDRESS D[7] 1 2 3 4 5 N-Divider MSB N-Divider LSB Charge Pump F-Divider MSB F-Divider LSB XTAL Divider R-Divider PLL VCO LPF Control Shutdown Test Status Byte-1 Status Byte-2 Write Write Write Write Write 0x00 0x01 0x02 0x03 0x04 FRAC 1 N[7] CPMP[1] 0 F[15] F[7] D[6] N[14] N[6] CPMP[0] 0 F[14] F[6] D[5] N[13] N[5] CPLIN[1] 0 F[13] F[5] DATA BYTE D[4] N[12] N[4] CPLIN[0] 0 F[12] F[4] D[3] N[11] N[3] F[19] F[11] F[3] D[2] N[10] N[2] F[18] F[10] F[2] D[1] N[9] N[1] F[17] F[9] F[1] D[0] N[8] N[0] F[16] F[8] F[0] LSB
6
Write
0x05
XD[2]
XD[1] CPS 0 VCO[3] LP[6] X PLL CPTST[1] 0 VASA
XD[0] ICP 1 VCO[2] LP[5] PWDN DIV CPTST[0] 0 VASE
R[4]
R[3]
R[2]
R[1]
R[0]
7 8 9 10 11 12
Write Write Write Write Write Write
0x06 0x07 0x08 0x09 0x0A 0x0B
D24 VCO[4] LP[7] STBY X CPTST[2] 0 POR
X VCO[1] LP[4] X VCO X
X VCO[0] LP[3] BBG[3] BB TURBO 1 X
X VAS LP[2]
X ADL LP[1]
X ADE LP[0]
BBG[2] BBG[1] BBG[0] RFMIX RFVG FE LD LD LD MUX[2] MUX[1] MUX[0] 0 0 0 X X X
13 14
Read Read
0x0C 0x0D
LD
VCOSBR[4] VCOSBR[3] VCOSBR[2] VCOSBR[1] VCOSBR[0] ADC[2] ADC[1] ADC[0]
X = Don't care.
0 = Set to 0 for factory-tested operation.
1 = Set to 1 for factory-tested operation.
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Complete, Direct-Conversion Tuner for DVB-S2 Applications MAX2112
Table 2. N-Divider MSB Register
BIT NAME FRAC N[14:8] BIT LOCATION (0 = LSB) DEFAULT 7 6-0 1 0000000 FUNCTION Users must program to 1 upon powering up the device. Sets the most significant bits of the PLL integer-divide number (N). N can range from 19 to 251.
Table 3. N-Divider LSB Register
BIT NAME N[7:0] BIT LOCATION (0 = LSB) 7-0 DEFAULT 00100011 FUNCTION Sets the least significant bits of the PLL integer-divide number. N can range from 19 to 251.
Table 4. Charge-Pump Register
BIT NAME CPMP[1:0] CPLIN[1:0] F[19:16] BIT LOCATION (0 = LSB) 7-6 5-4 3-0 DEFAULT 00 00 0010 FUNCTION Charge-pump minimum pulse width. Users must program to 00 upon powering up the device. Controls charge-pump linearity. Users must program to 00 upon powering up the device. Sets the 4 most significant bits of the PLL fractional divide number. Default value is F = 194,180 decimal.
Table 5. F-Divider MSB Register
BIT NAME F[15:8] BIT LOCATION (0 = LSB) 7-0 DEFAULT 11110110 FUNCTION Sets the most significant bits of the PLL fractional-divide number (F). Default value is F = 194,180 decimal.
Table 6. F-Divider LSB Register
BIT NAME F[7:0] BIT LOCATION (0 = LSB) 7-0 DEFAULT 10000100 FUNCTION Sets the least significant bits of the PLL fractional-divide number (F). Default value is F = 194,180 decimal.
Table 7. XTAL Buffer and Reference Divider Register
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION Sets the crystal-divider setting. 000 = Divide by 1. 001 = Divide by 2. 011 = Divide by 3. 100 = Divide by 4. 101 through 110 = All divide values from 5 (101) to 7 (110). 111 = Divide by 8. Sets the PLL reference-divider (R) number. Users must program to 00001 upon powering up the device. 00001 = Divide by 1; other values are not tested.
XD[2:0]
7-5
000
R[4:0]
4-0
00001
10
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Complete, Direct-Conversion Tuner for DVB-S2 Applications
Table 8. PLL Register
BIT NAME D24 BIT LOCATION (0 = LSB) DEFAULT 7 1 VCO divider setting. 0 = Divide by 2. 1 = Divide by 4 (default). Charge-pump current mode. Users must program to 0 upon powering up the device. 0 = Charge-pump current controlled by ICP bit. 1 = Charge-pump current controlled by VCO autoselect (VAS). Charge-pump current. Users must program to 1 upon powering up the device. 0 = 600A typical. 1 = 1200A typical. Don't care. FUNCTION
MAX2112
CPS
6
0
ICP
5
0
X
4-0
X
Table 9. VCO Register
BIT NAME VCO[4:0] BIT LOCATION (0 = LSB) DEFAULT 7-3 11001 FUNCTION Controls which VCO is activated when using manual VCO programming mode. This also serves as the starting point for the VCO autoselection (VAS) mode. VCO autoselection (VAS) circuit. 0 = Disable VCO selection must be programmed through I2C. 1 = Enable VCO selection controlled by autoselection circuit. Enables or disables the VCO tuning voltage ADC latch when the VCO autoselect mode (VAS) is disabled. 0 = Disables the ADC latch. 1 = Latches the ADC value. Enables or disables VCO tuning voltage ADC read when the VCO autoselect mode (VAS) is disabled. 0 = Disables ADC read. 1 = Enables ADC read.
VAS
2
1
ADL
1
0
ADE
0
0
Table 10. Lowpass Filter Register
BIT NAME LPF[7:0] BIT LOCATION (0 = LSB) DEFAULT 7-0 FUNCTION Sets the baseband lowpass filter 3dB corner frequency. 01001011 f-3dB = 4MHz + (LPF[3:0]dec - 12) x 290kHz. Default value equates to f-3dB = 22.27MHz typical.
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Complete, Direct-Conversion Tuner for DVB-S2 Applications MAX2112
Table 11. Control Register
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION Software standby control. 0 = Normal operation. 1 = Disables the signal path and frequency synthesizer leaving only the 2-wire bus, crystal oscillator, XTALOUT buffer, and XTALOUT buffer divider active. Don't care. Software power-down control. 0 = Normal operation. 1 = Shuts down the entire chip, but leaves the 2-wire bus active and maintains the current register states. Don't care. Baseband gain setting (1dB typical per step). 0000 = Minimum gain (0dB, default). ... 1111 = Maximum gain (15dB typical).
STBY
7
0
X
6
X
PWDN
5
0
X
4
X
BBG[3:0]
3-0
0000
Table 12. Shutdown Register
BIT NAME X PLL BIT LOCATION (0 = LSB) DEFAULT 7 6 X 0 Don't care. PLL enable. 0 = Normal operation. 1 = Shuts down the PLL. Divider enable. 0 = Normal operation. 1 = Shuts down the divider. VCO enable. 0 = Normal operation. 1 = Shuts down the VCO. Baseband enable. 0 = Normal operation. 1 = Shuts down the baseband. RF mixer enable. 0 = Normal operation. 1 = Shuts down the RF mixer. RF VGA enable. 0 = Normal operation. 1 = Shuts down the RF VGA. Front-end enable. 0 = Normal operation. 1 = Shuts down the front-end. FUNCTION
DIV
5
0
VCO
4
0
BB
3
0
RFMIX
2
0
RFVGA
1
0
FE
0
0
12
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Complete, Direct-Conversion Tuner for DVB-S2 Applications
Table 13. Test Register
BIT NAME CPTST[2:0] X TURBO LDMUX[2:0] BIT LOCATION (0 = LSB) 7-5 4 3 2-0 DEFAULT 000 X 0 000 FUNCTION Charge-pump test modes. 000 = Normal operation (default). Don't care. Charge-pump fast lock. Users must program to 1 after powering up the device. REFOUT output. 000 = Normal operation. Other values are not tested.
MAX2112
Table 14. Status Byte-1 Register
BIT NAME BIT LOCATION (0 = LSB) FUNCTION Power-on reset status. 0 = Chip status register has been read with a stop condition since last power-on. 1 = Power-on reset (power cycle) has occurred. Default values have been loaded in registers. Indicates whether VCO autoselection was successful. 0 = Indicates the autoselect function is disabled or unsuccessful VCO selection. 1 = Indicates successful VCO autoselection. Status indicator for the autoselect function. 0 = Indicates the autoselect function is active. 1 = Indicates the autoselect process is inactive. PLL lock detector. 0 = Unlocked. 1 = Locked. Don't care.
POR
7
VASA
6
VASE
5
LD X
4 3:0
Table 15. Status Byte-2 Register
BIT NAME VCOSBR[4:0] BIT LOCATION (0 = LSB) 7-3 VCO band readback. VAS ADC output readback. 000 = Out of lock. 001 = Locked. 010 = VAS locked. 101 = VAS locked. 110 = Locked. 111 = Out of lock. FUNCTION
ADC[2:0]
2-0
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Complete, Direct-Conversion Tuner for DVB-S2 Applications MAX2112
2-Wire Serial Interface
The MAX2112 uses a 2-wire I2C-compatible serial interface consisting of a serial-data line (SDA) and a serialclock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX2112 and the master at clock frequencies up to 400kHz. The master initiates a data transfer on the bus and generates the SCL signal to permit data transfer. The MAX2112 behaves as a slave device that transfers and receives data to and from the master. SDA and SCL must be pulled high with external pullup resistors (1k or greater) for proper bus operation. One bit is transferred during each SCL clock cycle. A minimum of nine clock cycles is required to transfer a byte in or out of the MAX2112 (8 bits and an ACK/NACK). The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high and stable are considered control signals (see the START and STOP Conditions section). Both SDA and SCL remain high when the bus is not busy.
Slave Address The MAX2112 has a 7-bit slave address that must be sent to the device following a START condition to initiate communication. The slave address is internally programmed to 1100000. The eighth bit (R/W) following the 7-bit address determines whether a read or write operation occurs. The MAX2112 continuously awaits a START condition followed by its slave address. When the device recognizes its slave address, it acknowledges by pulling the SDA line low for one clock period; it is ready to accept or send data depending on the R/W bit (Figure 1).
SLAVE ADDRESS S SDA SCL 1 1 0 0 0 0 0 R/W ACK
1
2
3
4
5
6
7
8
9
START and STOP Conditions The master initiates a transmission with a START condition (S), which is a high-to-low transition on SDA while SCL is high. The master terminates a transmission with a STOP condition (P), which is a low-to-high transition on SDA while SCL is high. Acknowledge and Not-Acknowledge Conditions Data transfers are framed with an acknowledge bit (ACK) or a not-acknowledge bit (NACK). Both the master and the MAX2112 (slave) generate acknowledge bits. To generate an acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse. To generate a not-acknowledge condition, the receiver allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse, and leaves SDA high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master must reattempt communication at a later time.
WRITE DEVICE START ADDRESS 1100000 WRITE REGISTER ADDRESS 0x00
Figure 1. MAX2112 Slave Address Byte
Write Cycle When addressed with a write command, the MAX2112 allows the master to write to a single register or to multiple successive registers. A write cycle begins with the bus master issuing a START condition followed by the seven slave address bits and a write bit (R/W = 0). The MAX2112 issues an ACK if the slave address byte is successfully received. The bus master must then send to the slave the address of the first register it wishes to write to (see Table 1 for register addresses). If the slave acknowledges the address, the master can then write one byte to the register at the specified address. Data is written beginning with the most significant bit. The MAX2112 again issues an ACK if the data is successfully written to the register. The master can continue to write data to the successive internal registers with the MAX2112 acknowledging each successful transfer, or it can terminate transmission by issuing a STOP condition. The write cycle does not terminate until the master issues a STOP condition.
R/W 0
ACK --
ACK --
WRITE DATA TO REGISTER 0x00 0x0E
ACK --
WRITE DATA TO REGISTER 0x01 0xD8
ACK --
WRITE DATA TO REGISTER 0x02 0xE1
ACK --
STOP
Figure 2. Example: Write Registers 0 through 2 with 0x0E, 0xD8, and 0xE1, respectively.
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Complete, Direct-Conversion Tuner for DVB-S2 Applications MAX2112
START WRITE DEVICE ADDRESS 1100000 R/W 1 ACK -- READ FROM STATUS BYTE-1 REGISTER -- ACK -- READ FROM STATUS BYTE-2 REGISTER -- ACK/ NACK -- STOP
Figure 3. Example: Receive Data from Read Registers
Read Cycle There are only two registers on the MAX2112 that are available to be read by the master. When addressed with a read command, the MAX2112 sends back the contents of both read registers (Status Byte-1 and Status Byte-2). A read cycle begins with the bus master issuing a START condition followed by the seven slave address bits and a read bit (R/W = 1). If the slave address byte is successfully received, the MAX2112 issues an ACK. The master then reads the contents of the Status Byte-1 register, beginning with the most significant bit, and acknowledges if the byte is received successfully. Next, the master reads the contents of the Status Byte-2 register. At this point the master can issue an ACK or NACK and then a STOP condition to terminate the read cycle.
Total device supply current depends on the filter BW setting. See Supply Current vs. Baseband Filter Cutoff Frequency in the Typical Operating Characteristics for more information.
DC Offset Cancellation
The DC offset cancellation is required to maintain the I/Q output dynamic range. Connecting an external capacitor between IDC+ and IDC- forms a highpass filter for the I channel and an external capacitor between QDC+ and QDC- forms a highpass filter for the Q channel. Keep the value of the external capacitor less than 47nF to form a typical highpass corner of 250Hz.
XTAL Oscillator
The MAX2112 contains an internal reference oscillator, reference output divider, and output buffer. All that is required is to connect a crystal through a series 1nF capacitor. Use a crystal with an ESR less than 60 for a 27MHz crystal. The typical input capacitance is 16pF. Contact the factory for more information if not using a 27MHz crystal.
Application Information
The MAX2112 downconverts RF signals in the 925MHz to 2175MHz range directly to the baseband I/Q signals. The devices are targeted for digital DBS tuner applications.
RF Input
The RF input of the MAX2112 is internally matched to 75. Only a DC-blocking capacitor is needed. See the Typical Application Circuit.
VCO Autoselect (VAS)
The MAX2112 includes 24 VCOs. The local oscillator frequency can be manually selected by programming the VCO[4:0] bits in the VCO register. The selected VCO is reported in the Status Byte-2 register (see Table 15). Alternatively, the MAX2112 can be set to autonomously choose a VCO by setting the VAS bit in the VCO register to logic-high. The VAS routine is initiated once the F-Divider LSB register word (REG 5) is loaded. In the event that only the N-divider register or F-divider MSB word is changed, the F-divider LSB word must also be loaded last to initiate the VCO autoselect function. The VCO value programmed in the VCO[4:0] register serves as the starting point for the automatic VCO selection process. During the selection process, the VASE bit in the Status Byte-1 register is cleared to indicate the autoselection function is active. Upon successful completion, bits VASE and VASA are set and the VCO selected is reported in the Status Byte-2 register (see Table 15). If the search is unsuccessful, VASA is cleared and VASE is set. This indicates that searching has ended but no good VCO has been found, and occurs when trying to tune to a frequency outside the VCO's specified frequency range.
15
RF Gain Control
The MAX2112 features a variable-gain low-noise amplifier providing 73dB of RF gain range. The voltage control (VGC) range is 0.5V (minimum attenuation) to 2.7V (maximum attenuation).
Baseband Variable-Gain Amplifier
The receiver baseband variable-gain amplifiers provide 15dB of gain control range programmable in 1dB steps. The VGA gain can be serially programmed through the SPI interface by setting bits BBG[3:0] in the Control register.
Baseband Lowpass Filter
The MAX2112 includes a programmable on-chip 7th-order Butterworth filter. The filter -3dB corner frequency can be adjusted from approximately 4MHz to 40MHz by programming the LPF[7:0] register using the following equation: LPF[3:0]dec = (f-3dB - 4MHz) / 0.29MHz + 12, where f-3dB is in units of MHz.
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Complete, Direct-Conversion Tuner for DVB-S2 Applications MAX2112
Refer to the MAX2112/MAX2120 VCO Autoselect (VAS) Application Note for more information.
Power-Down and Standby Modes
The MAX2112 features normal operating mode, powerdown mode, and standby mode using the I2C interface. Setting a logic-high to the PWDN bit in the Control register enables power-down. In this mode, all circuitries except for the 2-wire-compatible bus are disabled, allowing for programming of the MAX2112 registers while in power-down. Setting a logic-high to the STBY bit in the Control register puts the device into standby mode, during which only the 2-wire-compatible bus, the crystal oscillator, the XTAL buffer, and the XTAL buffer divider are active. In all cases, register settings loaded prior to entering shutdown are saved upon transition back to active mode. Default register values are provided for the user's convenience only. It is the user's responsibility to load all the registers no sooner than 100s after the device is powered up. The various power-down modes are summarized in Table 17.
3-Bit ADC
The MAX2112 has an internal 3-bit ADC connected to the VCO tune pin (VTUNE). This ADC can be used for checking the lock status of the VCOs. Table 16 summarizes the ADC output bits and the VCO lock indication. The VCO autoselect routine only selects a VCO in the "VAS locked" range. This allows room for a VCO to drift over temperature and remain in a valid "locked" range. The ADC must first be enabled by setting the ADE bit in the VCO register. The ADC reading is latched by a subsequent programming of the ADC latch bit (ADL = 1). The ADC value is reported in the Status Byte-2 register (see Table 15).
Table 16. ADC Trip Points and Lock Status
ADC[2:0] 000 001 010 101 110 111 LOCK STATUS Out of lock Locked VAS locked VAS locked Locked Out of lock
Layout Considerations
The MAX2112 EV kit serves as a guide for PCB layout. Keep RF signal lines as short as possible to minimize losses and radiation. Use controlled impedance on all high-frequency traces. For proper operation, the exposed paddle must be soldered evenly to the board's ground plane. Use abundant vias beneath the exposed paddle for maximum heat dissipation. Use abundant ground vias between RF traces to minimize undesired coupling. Bypass each VCC pin to ground with a 1nF capacitor placed as close as possible to the pin.
CIRCUIT STATES SIGNAL PATH On Off Off 2-WIRE INTERFACE On On On XTAL On Off On DESCRIPTION All circuits active. 2-wire interface is active. 2-wire interface, XTAL, and XTAL buffer/divider are active.
Table 17. Power-Down Modes
POWER-DOWN CONTROL MODE Normal Power-Down Standby PWDN BIT 0 1 0 STBY BIT 0 0 1
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Complete, Direct-Conversion Tuner for DVB-S2 Applications
Typical Application Circuit
SERIAL-DATA INPUT/OUTPUT SERIAL-CLOCK INPUT VCC
MAX2112
VCC_BB
ADDR
QDC-
QDC+
VCC
+
VCC_RF2 1
28
27
SDA
26
25
24
23
IDC22 21 IOUT20 IOUT+
SCL
IDC+
VCC
VCC_RF1 2 GND RF INPUT
VGC VCC
INTERFACE LOGIC AND CONTROL
MAX2112
LPF BW CONTROL
DC OFFSET CORRECTION
3
19 QOUTBASEBAND OUTPUTS
RFIN GC1
4 5 DIV2 /DIV4 EP FREQUENCY SYNTHESIZER
18 QOUT+ 17 VCC_DIG REFOUT
VCC
VCC_LO
VCC
6
16
VCC_VCO 7 8 VCOBYP VTUNE 9 GNDTUNE 10 GNDSYN 11 12 CPOUT 13 VCC_SYN XTAL 14 15
VCC
Chip Information
PROCESS: BiCMOS
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Complete, Direct-Conversion Tuner for DVB-S2 Applications MAX2112
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
21-0140
K
1
2
18
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QFN THIN.EPS
Complete, Direct-Conversion Tuner for DVB-S2 Applications
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX2112
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
21-0140
K
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
(c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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